In order to protect integrated circuit (IC) devices against damage caused by electrostatic discharge (ESD), special device elements called ESD protection elements may be used. In this context, it may be useful to have ESD protection elements which may be compliant with an interface voltage in the range from about 5 V to 12 V for an input/output (I/O) circuit implemented in a system on chip (SoC). These SoC ICs may be produced in advanced CMOS (Complementary Metal Oxide Semiconductor) technologies where no gate oxides of appropriate thickness may be available. One option is to use so-called drain-extended MOS (DEMOS) devices for I/O drivers, which are asymmetric with respect to the drain and source construction. The specific drain construction in these devices may allow to drop the voltage along the drain to a lower, less critical value at the gate. However, these devices are known to be ESD-weak in general and a self-protection can hardly be achieved.
Concepts that have been or are used to protect high-voltage I/O circuits (Vsignal>5 V) of advanced CMOS ICs include the following:
Above 1 μm technology, thick-oxide or field-oxide devices have commonly been used. In those technologies, lateral parasitic NPN transistors were used for ESD protection. With technology scaling reaching the deep submicron and sub 100 nm regime, the performance of these protection devices degrades since in thin-oxide devices the breakdown voltage of an I/O device matches more closely to the trigger voltage of the protection device. In many cases, grounded-gate NMOS (ggNMOS) transistors are used, which are CMOS compatible. In sub 100 nm node technology, silicon controlled rectifiers (SCR) or thyristors have widely been used, but they are generally not CMOS process compatible which leads to higher cost. Stacked NMOS devices may be used for ESD protection, but they usually cannot survive high voltages due to junction breakdown effects.
Thin-oxide MOS field-effect transistors (MOSFET) connected in grounded-gate configuration form a lateral NPN transistor with Collector (formed by the Drain), Emitter (formed by the Source) and Base (formed by the Substrate) which may be used for ESD protection. In single-finger structures, triggering of the lateral NPN transistor for ESD protection may be relatively difficult to achieve, which commonly leads to an ESD performance below 2 kV (HBM: Human Body Model). By means of a proper gate-to-drain coupling (or through substrate pumping) to generate enough substrate current during ESD stress, the ESD level may be enhanced to more than 6 kV. Another possibility to achieve a sufficient level of ESD robustness may be the use of substrate and gate biasing.